Successful overclock

**Xmister** · 02-14-2011, 01:56 AM

First, you are looking at the wrong table, second I wasn't right in a few things.

So that's the default table:

static const u32 s3c_cpu_clk_tab_800MHz[][6] = {
{800*MHZ, 266 *MHZ, 400, 3, 0, 2},
{400*MHZ, 266 *MHZ, 400, 3, 1, 2},
{266*MHZ, 266 *MHZ, 400, 3, 2, 2},
{133*MHZ, 266 *MHZ, 400, 3, 5, 2},
#ifdef USE_DVFS_AL1_LEVEL
{133*MHZ, 133 *MHZ, 400, 1, 5, 5},
#endif /* USE_DVFS_AL1_LEVEL */
{ 66*MHZ, 133 *MHZ, 400, 1, 11, 5},
};

As we can see the freqs are calculated by some divisions, with a logic I don't know.
So you first have to calculate(or find in some documentation) that how the 133 is come from 400,3,5,2 and 66 from 400,1,11,5. Once you have the logic, you can calculate the right values for 33Mhz.

---------- Post added 02-14-2011 at 12:56 AM ---------- Previous post was 02-13-2011 at 07:31 PM ----------

I've got a tip in PM, how are these calculated (thanks to lennox671):

Originally Posted by lennox671

I don't have enough posts to reply to the thread, so i give you the tip by pm:

Code:
/* ARMCLK, HCLKX2, APLL, PDIV, ARM_DIV, HCLKX2_DIV */
static const u32 s3c_cpu_clk_tab_800MHz[][6] = {
{800*MHZ, 266 *MHZ, 400, 3, 0, 2},
{400*MHZ, 266 *MHZ, 400, 3, 1, 2},
{266*MHZ, 266 *MHZ, 400, 3, 2, 2},
{133*MHZ, 266 *MHZ, 400, 3, 5, 2},
#ifdef USE_DVFS_AL1_LEVEL
{133*MHZ, 133 *MHZ, 400, 1, 5, 5},
#endif /* USE_DVFS_AL1_LEVEL */
{ 66*MHZ, 133 *MHZ, 400, 1, 11, 5},
};
ARMCLK= 2 * APLL / (ARM_DIV + 1)

HCLKX2= 2 * APLL / (HCLKX2_DIV + 1) <= I don't know what this clock is for

When APLL is set to 400, to get 50MHz you have to set ARM_DIV to 15, but I don't know if you can get lower
(depends on the size of the ARM_DIV register ... )

So if you would like to get 33MHz, then in theory you should have the last line like this:

Code: